The present invention relates in general to very large-scale integrated circuits on single semiconductor chips, and more particularly relates to a system and methodology employing standardized on-chip bus definitions and virtual component interfaces.
In present-day integrated circuit design, it is commonplace to implement different circuits or components in a single semiconductor chip. Large-scale integration of this kind saves costs in assembly, can increase reliability, and generally increases overall system speed. On-chip buses are used to interconnect xe2x80x9cvirtualxe2x80x9d components (VCs; so-called because they are self-contained, perform distinct functions but are not implemented as physically separate devices) on single, multiple-function chips.
As designers have sought to implement more and more VCs on a single chip, the kinds and numbers of the several interconnecting on-chip buses have proliferated. Conventionally, there is no single bus which satisfies the requirements of every VC on the chip. Each conventional bus design has its own strengths and weaknesses. A need has therefore arisen on the part of systems integrators to develop an intercomponent connection methodology and VC interface that avoids a large number of buses and which can be used as a standard for VC designers and integrators.
According to the invention, a standard interface block (SI) is provided which enables system designers to mix and match virtual components from different vendors. Each virtual component, or VC, has a virtual component interface, often called a VCI. The VCI in turn communicates through the standard interface (xe2x80x9cSIxe2x80x9d) block to each interface. In this way, all virtual components implemented on the chip can communicate with each other using one or two buses of a predetermined, standardized design, and each VC+SI combination creates an encapsulated, reusable architectural component that can be mixed and matched with any other such architectural component while maintaining acceptable functionality and performance of the chip.
In a preferred embodiment, the system design has at least two buses: a system on-chip bus which has a large bandwidth and enhanced functionality, and a xe2x80x9cperipheralxe2x80x9d on-chip bus which has a definition that is a subset of the system on-chip bus. System VCs are connected through their system VCIs to the system on-chip bus, while the typically slower xe2x80x9cperipheralxe2x80x9d VCs are connected, as configured according to their respective peripheral VCIs, through respective SI blocks to the peripheral on-chip bus. A bridge is provided between the system and peripheral buses for communication between system and peripheral virtual components, and this bridge includes a standard SI block.
The present invention confers the following technical advantages. The interface according to the invention enables maximum portability of customer-designed VCs. Once made compliant with the protocol of the bus to which they will be connected, VCs do not require modification in order to connect to a different bus having this protocol. The system bus definition is a compatible superset of the peripheral bus definition, enhancing interoperability choices for the system designer and design opportunities for the VC designer. Optional signals are minimized in their number in order to minimize the complexity of VCI compliance checking.
In order to obtain these advantages, the preferred embodiment of the invention has the following characteristics. First, master/slave connections are point-to-point and unidirectional. Both multiplexed and tri-state on-chip buses can be supported by allowing the on-chip bus wrappers or SI blocks to implement the on-chip bus transceivers. Unidirectional buses are simpler to handle and circumvent the requirement for arbitration in the VCI protocol. Second, the master VC can only present requests, and the slave can only respond. If a VC requires both of these capabilities, then parallel master and slave interfaces are implemented in the VC and SI block. Read and write are the two fundamental requests. The peripheral VCI signal set is enhanced in the system VCI specification.
Third, only valid transfers should cross the VCI interface. The master VC sends only information that the linked slave VC can understand. This is mandated by the lack of an error or rejection mechanism, which the peripheral bus according to the invention intentionally avoids as being too complex.
Fourth, address/data widths are determined by VC requirements. The on-chip bus target master should scale its address/data widths to match the slave.
Fifth, the bus specification should insure that any required data and address storage in the bus wrappers is minimal.
Sixth, clock domain crossing should not be visible at the interface. The peripheral interface according to the invention is fully synchronous.
Seventh, the acknowledge (Ack) signal should be independent of anything outside of the control of the peripheral VC. This precludes the need for a time-out mechanism.